1. Field of the Invention
The present invention relates to a method for manufacturing an SOI wafer.
2. Description of the Related Art
According to current processes known in the microelectronics industry, the substrate of integrated devices is obtained from wafers of monocrystalline silicon. In the last few years, as an alternative to wafers consisting of silicon alone, composite wafers, so-called xe2x80x9cSOIxe2x80x9d (Silicon-on-Insulator) wafers have been proposed, comprising two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer (see for example the article xe2x80x9cSilicon-on-Insulator Wafer Bondingxe2x80x94Wafer Thinning Technological Evaluationsxe2x80x9d by J. Hausman, G. A. Spierings, U. K. P. Bierman and J. A. Pals, Japanese Journal of Applied Physics, Vol. 28, No. 8, August 1989, pp. 1426-1443).
Considerable attention has recently been paid to SOI wafers, since integrated circuits having a substrate formed from wafers of this type have considerable advantages compared with similar circuits formed on conventional substrates, formed by monocrystalline silicon alone. These advantages can be summarized as follows:
a) faster switching speed;
b) greater immunity to noise;
c) smaller loss currents;
d) elimination of parasitic component activation phenomena (latch-up);
e) reduction of parasitic capacitance;
f) greater resistance to radiation effects; and
g) greater component packing density.
A typical process for manufacturing SOI wafers is described in the aforementioned article, and is based on bonding two monocrystalline silicon wafers (wafer bonding process). In particular, according to this process, one wafer is oxidized, and after cleaning operations, it is bonded to the other wafer. After a thermal annealing step, the outer surface of the oxidized wafer is submitted to surface grinding, polishing until the required thickness is obtained (for example 1 xcexcm), and buffing. An epitaxial layer, integrating electronic components, is subsequently optionally grown on the thinner monocrystalline silicon layer.
The wafers obtained by the conventional wafer bonding method have excellent electrical features, but have undeniably high costs (approximately six times greater than the cost of the standard substrates).
Other methodologies, such as ZHR, SIMOX, etc., are described in the article xe2x80x9cSOI Technologies: Their Past, Present and Futurexe2x80x9d by J. Haisha, Journal de Physique, Colloque C4, Supplxc3xa9ment xc3xa1 no. 9, Tome 49, September 1988. These latter techniques have also not yet reached an acceptable industrial level, and have some limitations. In fact, they do not allow obtainment of monocrystalline silicon layers on extensive oxide areas, they have a high defect level owing to displacements generated by stresses induced by the covered oxide, or they do not allow application of high voltages as with SIMOX technology, wherein the oxide thickness obtained by oxygen implant is approximately 100-200 nm.
The present invention provides a process for manufacturing an SOI wafer which exploits at least some of the inherent advantages of these technologies, but at competitive costs with respect to standard, fully monocrystalline substrates now being used.
On a wafer of monocrystalline semiconductor material, first protective regions of an oxidation resistant material are formed, covering first wafer portions. Deep trenches are formed in said wafer, extending between and laterally delimiting said first wafer portions. Said first wafer portions are oxidized, except upper portions, forming at least one continuous region of covered oxide overlaid by said non-oxidised upper portions, and covered by said first protective regions. Said first protective regions are removed, and a crystalline semiconductor material layer is epitaxially grown from said upper portions.